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 HD75161A
Octal General Purpose Interface Bus Transceivers
REJ03D0309-0200Z (Previous ADE-205-591 (Z)) Rev.2.00 Jul.16.2004
Description
The HD75161A is an 8 channel general purpose interface bus transceiver designed to meet the requirements of IEEE standard 488-1978. The transceiver is to provide the bus management and data transfer signals during operating in a controller instrumentation system. When combined with the HD75160A octal bus transceiver, the HD75161A provides the complete 16 wire interface for the IEEE 488 bus. The HD75161A features eight driver receiver pairs connected in a front to back configureation to form input/output ports at both the bus and terminal sides. The direction of data through these driver receiver pairs is determined by the DC and TE enable signals. The device exhibits a high impedance to the bus when VCC = 0 V since the bus terminating resistors are built in. If featurs driver outputs which can handle loads up to 48 mA of sink current. Each receiver features p n p transistor inputs for high input impedance and guaranteed hysteresis of 400 mV for increased noise immunity.
Features
* Ordering Information
Part Name HD75161AP Package Type DILP-20 pin Package Code DP-20N, -20NEV P Package Abbreviation -- Taping Abbreviation (Quantity)
Pin Arrangement
TE 1 REN 2 IFC 3
GPIB I/O PORTS NDAC NRFD
20 VCC 19 REN 18 IFC 17 16
NDAC NRFD TERMINAL I/O PORTS
4 5
DAV 6 EOI 7 ATN 8 SRQ 9 GND 10
15 DAV 14 EOI 13 ATN 12 SRQ 11 DC
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 11
HD75161A
Table Of Abbreviation
DRIVERS Name DC TE ATN SRQ REN IFC EOI DAV NDAC NRFD Identity Direction Control Talk Enable Attention Service Request Remote Enable Interface Clear End Or Identify Data Valid Not Data Accepted Not Ready For Data Class Control Bus Management
Data Transfer
Function Table
Bus management Channels DC H H L L H L Controls TE H H L L L H H L H L X X ATN*1 ATN R T R T SRQ REN Controlled By DC T R T R R T R T R T R T IFC EOI T R R T R T T R R T Data transfer Channels DAV NDAC NRFD Controlled by TE R T T R R T T R
H : High level L : Low level X : Irrelevant R : Receiver T : Transmit Notes: 1. ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. 2. Direction of data transmittion is from the terminal side to the bus side and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions.
Absolute Maximum Ratings
Item Supply Voltage Input Voltage Output Current Power Dissipation (Ta = 25C) Operating Temperature Range Storage Temperature Range Note: VCC VIC IOL PT Topr Tstg Symbol 7 5.5 100 1150 0 to 70 -65 to +150 Rating V V mA mW C C Unit
1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.2.00, Jul.16.2004, page 2 of 11
HD75161A
Recommended Operating Conditions
Item Supply Voltage Output Current Bus Ports With 3 State Outputs Terminal Ports Output Current Bus Ports With 3 State Outputs Terminal Ports Operating Temperature Symbol VCC IOH IOL Topr Min 4.75 -- -- -- -- 0 Typ 5.00 -- -- -- -- -- Max 5.25 -5.2 -800 48 16 70 V mA A mA C Unit
Logic Diagram
DC TE
ATN
D R
ATN
EOI
D R
EOI
SRQ
D R
SRQ
TERMINAL I/O PORTS
REN
D R
REN
IFC
D R
IFC
DAV
D R
DAV
NDAC
D R
NDAC
NRFD
D R
NRFD
Rev.2.00, Jul.16.2004, page 3 of 11
GPIB I/O PORTS
HD75161A
DC Electrical Characteristics (Ta = 0 to 70C)
Item Input Voltage Input Clamp Voltage Hysteresis Bus Output Voltage Terminal Bus Terminal Bus Input Current Terminal Terminal And Symbol VIH VIL VCC 2 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 Max -- 0.8 -1.5 -- -- -- 0.5 0.5 100 20 Unit V V V V V A II = -18 mA IOH = -800 A IOH = -5.2 mA IOL = 16 mA IOL = 48 mA VI = 5.5 V VI = 2.7 V VI = 0.5 V Driver II(bus) = 0 Disabled II(bus) = -12 mA Driver VI(bus) = -1.5 V to 0.4 V Disabled VI(bus) = 0.4 V to 2.5 V VI(bus) = 2.5 V to 3.7 V VI(bus) = 3.7 V to 5 V VI(bus) = 5 V to 5.5 V A mA VCC = 0, VI(bus) = 0 V to 2.5 V Conditions
VIK -- VT+ - VT- 0.4 VOH VOL II IIH 2.7 2.5 -- -- -- -- -- 2.5 -- -1.3 0 -- 0 0.7
Control Inputs IIL Voltage at Bus Port VI/O (bus) Current Into Bus VCC ON Port II/O (bus)
-100 3.7 V -1.5 -- -3.2 +2.5 -3.2 2.5 2.5 40 -75 mA
Short Circuit Output Current Supply Voltage
VCC OFF Terminal Bus
IOS ICC CI/O (bus)
-- -15 -25 -- --
-125 100 mA -- pF
No Load TE, DC, low VCC = 5 V or 0 V, VI/O = 0 to 2 V, f = 1 MHz
Bus port Capacitance Note: 1. VCC = 5 V, Ta = 25C
Switching Characteristics (VCC = 5 V, Ta = 25C)
Item Propagation Delay Time Symbol tPLH tPHL tPLH Input Output Terminal BUS BUS TE DC Terminal BUS ATTN, EO1 REN, IFC TE DC and DAY Terminal Test Min Typ Max Unit Circuit Test Conditions -- 14 20 ns 1 CL = 30 pF -- -- -- -- -- -- -- -- -- -- -- 14 12 16 -- -- -- -- -- -- -- -- 20 20 22 60 45 60 55 55 50 45 55 4 2 3 RL = 38.3 to 2.3 V CL = 30 pF RL = 240 to 5 V CL = 15 pF RL = 480 to 0 V CL = 15 pF RL = 38.3 to 2.3 V CL = 15 pF RL = 3 k to 0 V CL = 15 pF RL = 280 to 5 V
tPHL Output Enable Time tZH Output Disable Time tHZ Output Enable Time tZL Output Disable Time tLZ Output Enable Time tZH Output Disable Time tHZ Output Enable Time tZL Output Disable Time tLZ
Rev.2.00, Jul.16.2004, page 4 of 11
HD75161A
Switching Time Test Method
1. tPLH, tPHL
2.3 V
R L= 38.3 Test Point C L= 30 pF
Waveforms-1
tr Terminal Input 10 % t PLH Bus Output 90 % 1.5 V 90 % 1.5 V 10 % t PHL VOH 2V 0.8 V VOL tf 3V 0V
Rev.2.00, Jul.16.2004, page 5 of 11
HD75161A 2. tPLH, tPHL
5V Test Point R L= 240
C L= 30 pF
Waveforms-2
tr Bus Input 10 % t PLH Terminal Output 90 % 1.5 V 90 % 1.5 V 10 % t PHL VOH 1.5 V 1.5 V VOL tf 3V 0V
Rev.2.00, Jul.16.2004, page 6 of 11
HD75161A 3. tZH, tHZ, tZL, tLZ
Test Point
2.3 V R L= 38.3 S2 R L= 480 S1
C L= 15 pF
Waveforms-3
tr Control Input 10 % 90 % 1.5 V 90 % 1.5 V 10 % tf 3V 0V
t ZH Bus Output S1 Closed S2 Open
t HZ 90 % 2V 0.8 V VOH
t ZL Bus Output S1 Open S2 Closed
t LZ 2.3 V 0.8 V 10 % VOL
Rev.2.00, Jul.16.2004, page 7 of 11
HD75161A 4. tZH, tHZ, tZL, tLZ
5V Test Point S2 R L= 280 R L= 3 k S1
C L= 15 pF
Waveforms-4
tr Control Input 10 % 90 % 1.5 V 90 % 1.5 V 10 % tf 3V 0V
t ZH Terminal Output S1 Closed S2 Open
t HZ 90 % 1.5 V 0V VOH
t ZL Terminal Output S1 Open S2 Closed
t LZ 5V 1.5 V 10 % VOL
Notes:
1. The pulse generator has the following characteristics: PRR = 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, Zout = 50 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
Rev.2.00, Jul.16.2004, page 8 of 11
HD75161A
Characteristics Of Driver And Receiver
(a) Driver Output (b) Driver Output
Low Level Output Voltage VOL (V)
High Level Output Voltage VOH (V)
5 4 3 2 1 0 0 -20 -40
Ta = 25 C V CC = 5.25 V 5.00 V 4.75 V
0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 V CC = 4.75 V
Ta = 25 C
V CC = 5.00 V V CC = 5.25 V
-60
-80 -100
40
50
High Level Output Current IOH (mA)
Low Level Output Current IOL (mA)
(c) Receiver Output
(d) Receiver Output
Low Level Output Voltage VOL (V)
High Level Output Voltage VOH (V)
5 4 3 2 1 0 0 -10 -20
0.5 0.4 0.3 0.2 0.1 0 V CC = 4.75 V
Ta = 25 C V CC = 5.25 V 5.00 V 4.75 V
Ta = 25 C
V CC = 5.00 V V CC = 5.25 V
-30
-40
-50
0
12
18
24
30
High Level Output Current IOH (mA)
Low Level Output Current IOL (mA)
Rev.2.00, Jul.16.2004, page 9 of 11
HD75161A
(e) Input / Output Characteristics at Receiver
High Level Output Voltage VOUT (V)
5 4 3 2 1 0 0 0.4 0.8 VT -
VCC = 5 V Ta = 25 C
VT +
1.2
1.6
2.0
High Level Input Voltage VIN (V)
Rev.2.00, Jul.16.2004, page 10 of 11
HD75161A
Package Dimensions
As of January, 2003
Unit: mm
24.50 25.40 Max 20 11
1 0.89
1.27 Max
10 1.30 7.62
7.00 Max 2.54 Min 5.08 Max
0.51 Min
6.30
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
Package Code JEDEC JEITA Mass (reference value)
DP-20N -- Conforms 1.26 g
Unit: mm
24.50 25.40 Max 20 11
1 0.89
1.27 Max
10 1.30 7.62
7.00 Max 2.54 Min 5.08 Max
0.51 Min
6.30
2.54 0.25
*0.48 0.08
*0.25 0.06 0 - 15
*NI/Pd/AU Plating
Package Code JEDEC JEITA Mass (reference value)
DP-20NEV -- Conforms 1.26 g
Rev.2.00, Jul.16.2004, page 11 of 11
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
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http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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